1. Field of the Invention
The present invention relates to a multi-layer wiring board and a manufacturing method thereof. In addition, the invention relates to a semiconductor device using the multi-layer wiring board and a manufacturing method thereof.
2. Description of the Related Art
In recent years, semiconductor devices formed by using TFTs (Thin Film Transistors) that includes polycrystalline semiconductor thin films as switching elements for a pixel portion or pixel driver circuits are actively studied and developed. Since such TFTs including polycrystalline semiconductor thin films have the advantages of high field effect mobility and the like, technologies for integrally forming a display device and a functional circuit on the same substrate are also under research and development. As for functional circuits, there are CPUs, image signal processing circuits, memories and the like. In order to improve a value of a semiconductor device, a high-performance functional circuit is required to be formed in a small area.
FIG. 8 is a mask layout of a functional circuit having a typical structure of a conventional semiconductor device using TFTs. In this case, a first wiring layer is used as a TFT gate wiring 1007 and lead wirings 1008 between TFTs while a second wiring layer is used as lead wirings 1009 between TFTs and a power supply wiring 1010. When constructing a high-performance functional circuit using wirings in two layers in this manner, the second wiring is used for wide wirings such as a power supply wiring as well as a lead wiring. Therefore, a layout area is expanded.
As a means for reducing a layout area of a functional circuit, there is a method for reducing the width of lead wirings and power supply wirings, or a method for reducing the diameter of contact holes. However, when the lead wirings and the power supply wirings are reduced in width, electric resistance is increased, leading to delays of signals or a voltage drop. This causes a malfunction of the circuit, a decrease in operating frequency and the like. In addition, when reducing the diameter of the contact holes, an electrical connection between the first wiring and the second wiring may result in a poor connection, which will cause a malfunction of the circuit. In order to form solid contact holes, a more accurate exposure system and etching system are required. However, it leads to an extraordinary cost increase. Thus, it is quite difficult to reduce the width of lead wirings and power supply wirings or reduce the diameter of contact holes.
Meanwhile, as for the development of a conventional LSI, an operating frequency has been improved by reducing a chip area using a multi-layer wiring technology in order to achieve higher performance. In the multi-layer wiring technology, specific wirings are used for a wiring for a unit cell, a wiring for each block in a functional circuit, a wiring connecting blocks, a power supply wiring, a ground wiring and the like. According to such multi-layer wiring technology, a wiring area can be reduced, and thus a chip area can be reduced. Accordingly, it is expected that the multi-layer wiring technology is efficiently applied to the manufacture of a functional circuit, which is integrated with a display device on a common substrate in view of reduction in area.